In the usual PCM (pulse-code-modulation) telephone or other telecommunication system, such a frame period may be divided into 32 time slots assigned to respective signal channels including, say, 30 voice channels and two service channels; thus, a group of 32 channels is allotted to each signal path. Each time slot generally has a duration of approximately 4 .mu.s equaling--with 8-bit coding of digitized voice samples--eight bit intervals of 500 ns duration. The temporal and/or spatial transposition enables the transfer of voice samples or supervisory signals from any incoming channel to any outgoing channel, on the same or a different signal path, communicating therewith.
A switching unit or symmetrical time-division matrix (STM) of this type has been disclosed, for example, in U.S. Pat. Nos. 4,093,827 and 4,154,982. As particularly described in the first one of these patents, a series/parallel converter concurrently receives during each time slot the serially arriving bits of respective bytes from eight incoming signal paths or junctions which are then transmitted in parallel, one byte at a time, to a speech memory for temporary storage in respective cells thereof. The readout from the memory, under the control of address instructions from an external source acting as a telephone marker, occurs by way of a serializer receiving the bits of each byte in parallel from the memory and delivering them sequentially, during a designated time slot, to the outgoing signal path or junction for which they are intended.
A switching unit as described in the above-identified application (now U.S. Pat. No. 4,386,425), whose disclosure is hereby incorporated by reference into our present application, comprises a first read/write memory which has cells for the temporary storage of all the code words arriving during one frame period over all incoming signal paths and which is provided with loading means connectable to the incoming paths for inscribing arriving code words in its cells in a predetermined order, under the control of associated timing means, during one or more writing phases of each time slot of a frame period; the memory is further provided with unloading means connectable to the outgoing paths for reading out all (or, possibly, less than all) the inscribed code words in a sequence based on routing information stored in a second read/write memory. A scan of the cells of the latter memory during reading phases also recurring at least once per time slot yields the addresses of the cells of the first memory whose contents are to be consecutively read out to respective outgoing channels by the unloading means during a frame period; this second memory has input means for receiving such routing information in a writing phase as well as output means controlled by the timing means for delivering that information to an address input of the first memory during the reading phases. The routing information remains stored in the second memory until replaced by new information supplied during a writing phase in response to instructions from an associated command unit which are fed to decoding means including circuitry responsive to certain of these instructions for supplementing a stored cell address with an inhibiting or "busy" bit that is transmissible by the output means of the second memory and the address input of the first memory to the corresponding cell of the latter for blocking the transfer of its contents to any outgoing signal path.
In a larger switching array including two or more switching units of this description, whose respective unloading means are connected in parallel (with the aid of OR gates) to the same set of outgoing signal paths, the availability of such an inhibiting bit allows the blocking of the readout from any switching unit during one or more frame periods or during individual time slots thereof whereby these outgoing paths may selectively receive code words from different sets of incoming signal paths respectively terminating at the several units. The readout of an individual switching unit may also be blocked for the duration of a frame period in the event of an interruption of normal operation and initiation of a new microprogram.